In the field of semiconductor manufacturing, fine processing is nowadays close to physical limits. As a solution to overcome such physical limits, it has been proposed to realize high integration of semiconductor devices, in particular NAND flash memories, by stacking device components in height directions. The research and development of three-dimensional NAND flash memories etc. are being actively pursued using the proposed high-integration techniques.
One such type of three-dimensional NAND flash memory is disclosed in e.g. Toshiba Review, Vol. 66, No. 9, pages 16-19 (2011) (hereinafter referred to as “Non-Patent Document 1”). For manufacturing of this three-dimensional NAND flash memory, a laminated film is first formed as a charge holding part by alternately laminating a plurality of layers 1 of polycrystal silicon (abbreviated as “poly-Si” or “p-Si”) and a plurality of layers 2 of silicon oxide (abbreviated as “SiOx”) on a substrate as shown in FIG. 1. Next, through holes are formed by etching in the laminated film for embedding of interconnection between independent memory cells. More specifically, the etching is performed by applying a resist mask 3 with predetermined openings to the outmost layer of the laminated film and removing p-Si and SiOx upon contact with a plasma of fluorine-containing gas through the openings of the resist mask 3 in a chamber. Herein, the direction of collision of ions in the plasma is controlled with the application of a direct-current voltage, called “bias voltage”, between upper and lower electrodes in the chamber such that the laminated film is anisotropically etched in its height direction perpendicular to the in-plane direction (film surface direction). Although the bias voltage corresponds to a potential difference naturally occurring between the upper and lower electrodes due to the difference in migration speed between the ions and electrons in the plasma, the bias voltage can be adjusted with the supply of alternating-current power from an external source.
However, the preferable etching conditions of p-Si and SiOx differ from each other. In view of these different p-Si and SiOx etching conditions, it has been proposed in Toshiba Review, Vol. 66, No. 5, pages 29-33 (2011) (hereinafter referred to as “Non-Patent Document 2”) to form the through holes in the p-Si/SiOx laminated film by alternately and independently repeating p-Si etching operation and SiOx etching operation.
Further, there are widely used saturated fluorocarbons such as CF4, C2F6 and C3F8 as fluorine-containing etching gas components as disclosed in Japanese Translation of PCT International Application Publication No. JP-T-2007-537602 (hereinafter referred to as “Patent Document 1”). The use of such a saturated fluorocarbon however often results in the occurrence of etching in an undesired direction, called “side etching”. In the case of forming a through hole in a target layer 5 by etching through a mask 6 as shown in FIG. 2, for example, the etching of the target layer 5 may proceed in not only a vertical direction but also a horizontal direction so that the through hole becomes wider in diameter than the opening pattern of the mask 6 due to side etching 7.
Furthermore, Japanese Translation of PCT International Application Publication No. JP-T-2001-517868 (hereinafter referred to as “Patent Document 2”) discloses a plasma etching method for etching silicon oxide selectively over silicon nitride with the use of hexafluoropropylene (C3F6), octafluoropropane (C3F8), heptafluoropropane (C3HF7) or hexafluoropropane (C3H2F6).
Japanese Translation of PCT International Application Publication No. JP-T-2002-530863 (hereinafter referred to as “Patent Document 3”) discloses a plasma etching method for selectively etching a silicon oxide layer on a silicon nitride layer with the use of hexafluorobutadiene, hexafluorocyclobutene or hexafluorobenzene.
Japanese Laid-Open Patent Publication No. 2013-70012 (hereinafter referred to as “Patent Document 4”) discloses a dry etching method for a laminated film in which silicon layers and silicon oxide films are laminated together and, more specifically, for etching parts of the silicon layers appearing on an inner side surface of a hole or groove of the laminated film with the combined use of a fluorinated halogen compound gas and a fluorine gas.
On the other hand, Japanese Laid-Open Patent Publication No. 2011-176291, No. 2012-114402 and No. 2013-30531 (hereinafter referred to as “Patent Documents 5, 6 and 7”, respectively) disclose that the use of an unsaturated hydrofluorocarbon such as C3H2F4 or C3HF3 as an etching agent makes it possible to prevent the occurrence of side etching.
Japanese Laid-Open Patent Publication No. 2008-177209 (hereinafter referred to as “Patent Document 8”) discloses a plasma etching method for anisotropically etching a silicon substrate with the use of an etching gas containing iodine fluoride.